1. Field of the Invention
The present invention relates to receivers for use in a system in which a pixel clock required for video data reproduction is transmitted from a transmitter to a receiver, and more particularly, the invention relates to a receiver capable of generating an audio reference clock required for audio data reproduction.
2. Description of the Background Art
In recent years, standards called DVI (Digital Visual Interface), HDMI (High Definition Multimedia Interface), and LVDS (Low Voltage Differential Signaling) have been used as universal display interface standards. In these standards, the transmitter transmits video data and a pixel clock to the receiver in the form of a digital signal without modification. The receiver reproduces the video data based on the transmitted pixel clock.
FIG. 19 is a block diagram illustrating a general system concept where data is transmitted from a transmission-side electronic device 900 to a reception-side electronic device 903 in accordance with a standard as described above. In FIG. 19, the transmission-side electronic device 900 includes a data source 901 and a transmitter 902. Video and audio data outputted by the data source 901 is inputted to the transmitter 902, and converted into serial digital signals Tx0, Tx1, and Tx2. The transmitter 902 transmits the serial digital signals Tx0, Tx1, and Tx2 to a receiver 904, along with a pixel clock Txc outputted by the data source 901. The digital signals Tx0, Tx1, and Tx2 and the pixel clock Txc are transferred to the receiver 904 via a dedicated cable 906. The receiver 904 reproduces the video and audio data outputted by the data source 901 based on the digital signals Tx0, Tx1, and Tx2 and the pixel clock Txc, and sends the reproduced data to an output portion 905. The output portion 905 outputs image and audio based on the digital data from the receiver 904.
FIG. 20 is a block diagram illustrating features of a system according to the HDMI standard that are used for generating an audio reference clock required for audio data reproduction (see FIG. 15 and paragraphs [0268] to [0272] of Japanese National Phase PCT Laid-Open Publication No. 2005-514836). In FIG. 20, the transmitter 902 includes a register 907, a frequency divider 908, a cycle time counter 909, and a transmission portion 910. The transmitter 902 receives a pixel clock, an audio reference clock with a frequency of 128×Fs, and a natural number N. Here, Fs is a sampling frequency of, for example, 44.1 kHz or 48.0 kHz. The register 907 temporarily stores the natural number N. The frequency divider 908 divides the audio reference clock at a dividing ratio of 1/N based on the natural number N being temporarily stored in the register 907, thereby generating an intermediate clock, which is inputted to the cycle time counter 909. The cycle time counter 909 counts the number of pixel clocks during each cycle period of the intermediate clock, and outputs the count result as a CTS (Cycle Time Stamp). The transmission portion 910 transmits the pixel clock to the receiver 904 via a physical layer, and if necessary, properly transmits CTS and N in packets to the receiver 904.
By using such an architecture in the transmitter 902, a rational relationship is established between the pixel clock and the audio reference clock. When dividing the pixel clock frequency (fTMDS_clock) by the audio reference clock frequency (128×Fs), the denominator is N, and the numerator is CTS.
That is, the following relationship is established:128×Fs=(fTMDS_clock×N)/CTS. 
Also, the cycle time counter 909 uses CTS as a value for the number of pixel clocks counted during each cycle period of the intermediate clock, and therefore fTMDS_clock is divisible by CTS.
The receiver 904 includes a reception portion 911, a frequency divider 912, and a multiplier 913. The receiver 911 reproduces the pixel clock, CTS, and N. The frequency divider 912 divides the pixel clock at a dividing ratio of 1/CTS to reproduce and input the intermediate clock to the multiplier 913. FIG. 21 is a block diagram illustrating a detailed functional configuration of the multiplier 913 in the receiver 904. The multiplier 913 includes a phase detector 914, a low-pass filter 915, a voltage-controlled oscillator 916, and a frequency divider 917. The voltage-controlled oscillator 916 has an oscillating frequency set to be N times the frequency of the intermediate clock outputted by the frequency divider 912. The frequency divider 917 with a dividing ratio of 1/N divides and feeds back the output of the voltage-controlled oscillator 916. The PLL (phase-locked loop) circuit thus formed multiplies the frequency of the intermediate clock by N. Thus, the multiplier 913 can output an audio reference clock with a frequency of 128×Fs. In this manner, the HDMI standard employs the architecture capable of generating the audio reference clock based on the pixel clock.
Note that Japanese Laid-Open Patent Publication No. 10-233680 describes a diffusion-type fractional frequency divider in which a dividing number defined by the ratio of an input frequency to an output frequency is changed between two states of M and M+1, and a time point when the dividing number becomes M+1 is controlled based on random numbers or sequential numbers similar to the random numbers. Thus, the diffusion-type fractional frequency divider can provide an output signal with reduced spurious components.
Also, Japanese Laid-Open Patent Publication No. 2005-33581 describes a fractional-N frequency synthesizer including a feedback circuit taking advantage of the absence of periodicity in an output signal of a ΔΣ modulation circuit. Other examples of the related art for adjusting the dividing ratio using a ΔΣ modulation circuit include technologies as described in the specifications of U.S. Pat. Nos. 6,044,124 and 7,049,852.
Also, general information about audio reference clock reproduction according to the HDMI standard is described in Japanese Laid-Open Patent Publication Nos. 2007-13853 and 2007-150855, as well as in “High-Definition Multimedia Interface Specification Version 1.3a”, pp. 98 to 111, Nov. 10, 2006, Hitachi, Ltd., Matsushita Electric Industrial Co., Ltd., Philips Consumer Electronics, International B.V., Silicon Image, Inc., Sony Corporation, Thomson Inc., Toshiba Corporation.
For example, a case is considered where the pixel clock frequency is 74.25 MHz, the sampling frequency is 48.0 kHz, the audio reference clock frequency is 128×48.0 kHz, N is 6144, and CTS is 74250. In this case, the intermediate clock outputted by the frequency divider 912 is at a frequency of 1 kHz. In this manner, when a conventional HDMI architecture is used, the intermediate clock, i.e., the reference signal for the PLL circuit is at low frequency. Accordingly, to remove noise from the reference signal, it is necessary to lower the cut-off frequency of the low-pass filter in the PLL circuit. When the cut-off frequency of the low-pass filter is low, the filter has a large multiplier factor, making it difficult to achieve an on-chip low-pass filter.
Also, in the manufacturing stage, it is often the case that an audio test is performed at around 1 kHz. When the reference frequency is at around 1 kHz, there is a possibility where noise in the reference signal is outputted as audio during the test, thereby undesirably rendering the test inaccurate. Furthermore, it is also undesirable that the noise be present not only at around 1 kHz but also in an audio band (e.g., 20 Hz to 20 kHz). Accordingly, it is necessary to increase the reference frequency, thereby keeping noise out of the audio band, and also to use a cut-off frequency higher than the audio band, thereby cutting off noise.
Also, when the reference frequency is at around 1 kHz, and noise in the reference signal cannot be removed appropriately, jitter in the audio reference clock increases, which can lead to inaccurate audio data reproduction.